ROM: 448 KiB
For booting and core functions.
SRAM: 520 KiB
For data and instruction.
RTC Slow SRAM: 8 KiB
For co-processor accessing during deep-sleep mode.
RTC Fast SRAM: 8 KiB
For data storage and main CPU during RTC Boot from the deep-sleep mode.
eFuse: 1 Kibit
Of which 256 bits are used for the system (MAC address and chip configuration) and the remaining 768 bits are reserved for customer applications, including Flash-Encryption and Chip-ID.
Embedded Flash: 0 MiB or 2 MiB (depending on variation)
ESP32-D2WD has 2 MiB of embedded flash, internally connected via GPIO16, GPIO17, SD_CMD, SD_CLK, SD_DATA_0 and SD_DATA_1. The other chips in the ESP32 series have no embedded flash.
External Flash and SRAM: ESP32 without embedded flash supports up to 4 × 16 mebibytes of external QSPI flash and SRAM with hardware encryption based on AES to protect developer's programs and data.
Peripheral Input/Output: Rich peripheral interface with DMA that includes capacitive touch, ADCs (analog-to-digital converter), DACs (digital-to-analog converter), I²C (Inter-Integrated Circuit), UART (universal asynchronous receiver/transmitter), CAN 2.0 (Controller Area Network), SPI (Serial Peripheral Interface), I²S (Integrated Inter-IC Sound), RMII (Reduced Media-Independent Interface), PWM (pulse width modulation), and more.
IEEE 802.11 standard security features all supported, including WFA, WPA/WPA2 and WAPI
1024-bit OTP, up to 768-bit for customers
Cryptographic hardware acceleration: AES, SHA-2, RSA, elliptic curve cryptography (ECC), random number generator (RNG)